搜索资源列表
Xilinxopensourcecode
- xilinx公司的开放的源码，很有参考价值，其中有ddl，fifo控制等。
v2_fifo_vhd_258
- 这是一个基于xilinx ISE9.1的一个历程，包含两个FIFO代码，第一个FIFO读写用同一个时钟，第二个FIFO读写用不同的时钟。
sfifo_srl
- 针对XILINX FPGA特有的SRLC16E器件，实现的同期FIFO. 特点：宽度深度可配置，面积小。-SRLC16E Based Synthesise FIFO Implement by Xilinx FPGA. The Size is small and FIFO Width, Length can be configured.
ddr_usb
- 将256位数据宽度 通过两级FIFO 转成16位 使用XILINX的ISE10.1完成设计 此为工程文件 有仿真结果-The 256-bit data width conversion FIFO through the two 16-bit using the XILINX s ISE10.1 to complete the design documents for the works in this simulation results
sync_srl_fifo
- 适合xilinx FPGA的同步fifo-Synchronous fifo for xilinx FPGA
IPcore_fifo_testbench
- 我自己写的一个verilog的fifo测试程序，配合xilinx的fifo ip核-I own the fifo write a verilog test procedures, with the fifo ip nuclear xilinx
VHD
- 此为基于Xilinx的FPGA用VHDL实现的FIFO，已调通，可直接运行。-This is based on Xilinx FPGA using VHDL implementation of the FIFO, has been transferred through, can be directly run.
fifosy
- 用于对Xilinx FPGA FIFO的控制及读写-Xilinx FPGA FIFO
rx_fifo
- verilog语言写的接收机FIFO，适用于xilinx环境-verilog language to write the receiver FIFO, the environment for xilinx
sp3e_fifo
- xilinx spartan3e fifo读写测试工程 仿真通过。全套工程。-xilinx spartan3e fifo read and write test engineering simulation through.
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.
fifo_1
- 本程序是基于Xilinx的FPGA简单代码编写，对fifo的ip核进行简单的配置，并通过仿真代码进行仿真观察fifo的特性，适用于FPGA初学者。-This procedure is based on Xilinx' s FPGA simple code written for the ip nuclear fifo simple configuration, and Simulation observed through simulation code fifo for FPGA beg
HWL_ASYNC_FIFO_DRAM_BA
- asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
rim_top
- this is source usinf fifo source xilinx thank you.........................